The performance and reliability of thin film field effect transistors (TFTs) and solar cells that are fabricated in poly-crystalline (poly-Si) and amorphous (a-Si) silicon are limited by defects in these materials. Defects in poly-Si are primarily located in high defect density regions near interfaces and grain boundaries. Defects in a-Si are spatially distributed more uniformly than in poly-Si, though very high defect density regions can be found at interfaces between deposited layers. In TFTs, these defects provide sites for unwanted generation of carriers and result in a current flow, even when the TFT is in an off-state. These defects can also adversely affect device performance in the on-state.
Poly-Si TFTs offer not only superior field effect mobility over a-Si TFTs, but also exhibit the best overall combination of properties. However, when such poly-Si TFTs are utilized with large area displays, their off-current characteristics tend to reduce the contrast of the display. More specifically, even in the off-state, such poly-Si TFTs exhibit a current flow. Thus, when poly-Si TFTs are used to drive a large size display, such off-state current can enable the slow discharge of a capacitive charge previously applied across a display cell, such as a liquid crystal cell.
Further, as the off-state current in poly-Si TFTs is often voltage dependent, substantial efforts must be taken to set the applied off-state bias voltage within a narrow range to establish the lowest levels of off-state current.
Referring to FIG. 1, a schematic sectional diagram of a TFT 10 is illustrated that is deposited on a glass or plastic substrate 11. The particular configuration shown is a so-called top gate structure with a thin crystalline silicon layer 12 residing on a glass substrate 11 (which may or may not be coated) and, in the known manner, includes source and drain regions 14 and 16, respectively. A gate 18 is isolated from a conduction channel 20 via a dielectric layer 22.
Assuming that TFT 10 is doped to have a P-type conduction channel 20, then in a "forward biasing" mode of operation, Vs can be at ground and Vd at some negative voltage. In the off-state, a voltage +Vg, exhibiting a positive value must be applied to gate 18. Accordingly, a rather large electric field is created between gate 18 and drain region 16 in the off state. That field can enable electron-hole pairs to be created near the drain by a mechanism such as tunneling assisted generation. The resulting electrons (in the case of a P-channel TFT) can flood the channel. Such carriers enable an off-state current flow, since source and drain regions 14 and 16 are still biased to enable conduction, should carriers be present in conduction channel 20.
These generation mechanisms in the off-state are believed to occur via defects states. However, in a single crystal device, there is a low defect density and thus, a low value of off-state current. But in poly-Si TFTs, silicon layer 12 comprises a multi-crystalline structure which exhibits a substantial population of defects. Accordingly, the off-state current exhibits a higher value in multi-crystalline TFTs. Finally, a TFT's off-state current is voltage dependent and exhibits a changing value with changes in the off state bias voltage (i,e., between gate 18 and drain region 16).
It is known that the off-state field occurring between a drain and gate structure can be shaped by alteration of the doping of the drain region. Such action generally requires an angular implant (in addition to the original drain implant) to create a lightly doped drain region which reduces the strength of the off-state field. Because a second implant action is required to achieve the lightly doped drain region, expense is added as a result of the additional implant action.
Accordingly, it is an object of this invention to provide a means for reducing off-state current in a TFT.
It is another object of this invention to provide a method for tailoring the off-state current in a TFT which reduces the voltage dependency thereof.